--------------------------------------------------------------------
-- Register bank																--
--	myCPU																				--
-- Prof. Max Santana																--
--------------------------------------------------------------------

library ieee ;
use ieee.std_logic_1164.all;

entity registers is
  port(	
    clock   : in std_logic;
	 reset   : in std_logic;
	 rr1   	: in std_logic_vector(4 downto 0);  -- read register 1
	 rr2   	: in std_logic_vector(4 downto 0);  -- read register 2
	 rw   	: in std_logic;  							 -- read or write
	 wr   	: in std_logic_vector(4 downto 0);   -- register for write
    wd 		: in std_logic_vector(31 downto 0);  -- write data
    rd1		: out std_logic_vector(31 downto 0); -- read data 1
	 rd2		: out std_logic_vector(31 downto 0) -- read data 2
);
end registers;

architecture behv of registers is

  signal zero	: std_logic_vector(31 downto 0);
  signal at		: std_logic_vector(31 downto 0);
  signal v0		: std_logic_vector(31 downto 0);
  signal v1		: std_logic_vector(31 downto 0);
  signal a0		: std_logic_vector(31 downto 0);
  signal a1		: std_logic_vector(31 downto 0);
  signal a2		: std_logic_vector(31 downto 0);
  signal a3		: std_logic_vector(31 downto 0);
  signal t0		: std_logic_vector(31 downto 0);
  signal t1		: std_logic_vector(31 downto 0);
  signal t2		: std_logic_vector(31 downto 0);
  signal t3		: std_logic_vector(31 downto 0);
  signal t4		: std_logic_vector(31 downto 0);
  signal t5		: std_logic_vector(31 downto 0);
  signal t6		: std_logic_vector(31 downto 0);
  signal t7		: std_logic_vector(31 downto 0);
  signal s0		: std_logic_vector(31 downto 0);
  signal s1		: std_logic_vector(31 downto 0);
  signal s2		: std_logic_vector(31 downto 0);
  signal s3		: std_logic_vector(31 downto 0);
  signal s4		: std_logic_vector(31 downto 0);
  signal s5		: std_logic_vector(31 downto 0);
  signal s6		: std_logic_vector(31 downto 0);
  signal s7		: std_logic_vector(31 downto 0);
  signal t8		: std_logic_vector(31 downto 0);
  signal t9		: std_logic_vector(31 downto 0);
  signal k0		: std_logic_vector(31 downto 0);
  signal k1		: std_logic_vector(31 downto 0);
  signal gp		: std_logic_vector(31 downto 0);
  signal sp		: std_logic_vector(31 downto 0);
  signal fp		: std_logic_vector(31 downto 0);
  signal ra		: std_logic_vector(31 downto 0);
  
begin

  with rr1 select
    rd1 <= zero	when "00000",	
           at		when "00001",
           v0  	when "00010",
           v1  	when "00011",
	        a0  	when "00100",
    	     a1  	when "00101",
        	  a2  	when "00110",
           a3  	when "00111",
           t0  	when "01000",
	        t1  	when "01001",
    	     t2 		when "01010",
        	  t3 		when "01011",
           t4 		when "01100",
           t5 		when "01101",
	        t6 		when "01110",
    	     t7 		when "01111",
           s0 		when "10000",
           s1 		when "10001",
           s2 		when "10010",
           s3 		when "10011",
	        s4 		when "10100",
    	     s5 		when "10101",
        	  s6 		when "10110",
           s7 		when "10111",
           t8 		when "11000",
	        t9 		when "11001",
    	     k0 		when "11010",
        	  k1 		when "11011",
           gp 		when "11100",
           sp 		when "11101",
	        fp 		when "11110",
    	     ra 		when "11111";

  with rr2 select
    rd2 <= zero	when "00000",	
           at		when "00001",
           v0  	when "00010",
           v1  	when "00011",
	        a0  	when "00100",
    	     a1  	when "00101",
        	  a2  	when "00110",
           a3  	when "00111",
           t0  	when "01000",
	        t1  	when "01001",
    	     t2 		when "01010",
        	  t3 		when "01011",
           t4 		when "01100",
           t5 		when "01101",
	        t6 		when "01110",
    	     t7 		when "01111",
           s0 		when "10000",
           s1 		when "10001",
           s2 		when "10010",
           s3 		when "10011",
	        s4 		when "10100",
    	     s5 		when "10101",
        	  s6 		when "10110",
           s7 		when "10111",
           t8 		when "11000",
	        t9 		when "11001",
    	     k0 		when "11010",
        	  k1 		when "11011",
           gp 		when "11100",
           sp 		when "11101",
	        fp 		when "11110",
    	     ra 		when "11111";

  process (clock, reset)
  begin
			
    if(reset = '1') then
	   zero  <= "00000000000000000000000000000000";
		at  	<= "00000000000000000000000000000000";
		v0  	<= "00000000000000000000000000000000";
		v1  	<= "00000000000000000000000000000000";
		a0  	<= "00000000000000000000000000000000";
		a1  	<= "00000000000000000000000000000000";
		a2  	<= "00000000000000000000000000000000";
		a3  	<= "00000000000000000000000000000000";
		t0  	<= "00000000000000000000000000000000";
		t1  	<= "00000000000000000000000000000000";
		t2 	<= "00000000000000000000000000000000";
		t3 	<= "00000000000000000000000000000000";
		t4 	<= "00000000000000000000000000000000";
		t5 	<= "00000000000000000000000000000000";
		t6 	<= "00000000000000000000000000000000";
		t7 	<= "00000000000000000000000000000000";
		s0 	<= "00000000000000000000000000000000";
		s1 	<= "00000000000000000000000000001010";
		s2 	<= "00000000000000000000000000000000";
		s3 	<= "00000000000000000000000000000000";
		s4 	<= "00000000000000000000000000000000";
		s5 	<= "00000000000000000000000000000000";
		s6 	<= "00000000000000000000000000000000";
		s7 	<= "00000000000000000000000000000000";
		t8 	<= "00000000000000000000000000000000";
		t9 	<= "00000000000000000000000000000000";
		k0 	<= "00000000000000000000000000000000";
		k1 	<= "00000000000000000000000000000000";
		gp 	<= "00000000000000000000000000000000";
		sp 	<= "00000000000000000000000000000000";
		fp 	<= "00000000000000000000000000000000";
		ra 	<= "00000000000000000000000000000000";
			
    elsif (clock = '1' and clock'event) then
      if(rw = '1') then		
		  case wr is
		    when "00000" =>	zero  <= "00000000000000000000000000000000";
			 when "00001" =>	at	   <= wd;
			 when "00010" =>	v0  	<= wd;
			 when "00011" =>	v1  	<= wd;
			 when "00100" =>	a0  	<= wd;
			 when "00101" =>	a1  	<= wd;
			 when "00110" =>	a2  	<= wd;
			 when "00111" =>	a3  	<= wd;
			 when "01000" =>	t0  	<= wd;
			 when "01001" =>	t1  	<= wd;
			 when "01010" =>	t2 	<= wd;
			 when "01011" =>	t3 	<= wd;
			 when "01100" =>	t4 	<= wd;
			 when "01101" =>	t5 	<= wd;
			 when "01110" =>	t6 	<= wd;
			 when "01111" =>	t7 	<= wd;
			 when "10000" =>	s0 	<= wd;
			 when "10001" =>	s1 	<= wd;
			 when "10010" =>	s2 	<= wd;
			 when "10011" =>	s3 	<= wd;
			 when "10100" =>	s4 	<= wd;
			 when "10101" =>	s5 	<= wd;
			 when "10110" =>	s6 	<= wd;
			 when "10111" =>	s7 	<= wd;
			 when "11000" =>	t8 	<= wd;
			 when "11001" =>	t8 	<= wd;
			 when "11010" =>	k0 	<= wd;
			 when "11011" =>	k1 	<= wd;
			 when "11100" =>	gp 	<= wd;
			 when "11101" =>	sp 	<= wd;
			 when "11110" =>	fp 	<= wd;
			 when "11111" =>	ra 	<= wd;
        end case;
      end if;
    end if;
  end process;
 
			  
end behv;