--------------------------------------------------------------------
-- 32 bit register																--
--	myCPU																				--
-- Prof. Max Santana																--
--------------------------------------------------------------------

library ieee ;
use ieee.std_logic_1164.all;

entity reg32 is
  port(	
    d     	: in std_logic_vector(31 downto 0);
    clock 	: in std_logic;
    reset 	: in std_logic;
	 load 	: in std_logic;
    q			: out std_logic_vector(31 downto 0)
);
end reg32;

architecture behv of reg32 is
begin

  process(clock, reset, d)
  begin
    if (reset = '1') then
      q <= (q'range => '0');
	 elsif (clock = '1' and clock'event) then
	   if (Load = '1') then
	     q <= d;
		end if;
	 end if;
  end process;

end behv;