--------------------------------------------------------------------
-- 3:1 multiplexor																--
--	myCPU																				--
-- Prof. Max Santana																--
--------------------------------------------------------------------

library ieee ;
use ieee.std_logic_1164.all;

entity mux3 is
  port(	
    i0   : in std_logic_vector(31 downto 0);
	 i1   : in std_logic_vector(31 downto 0);
	 i2   : in std_logic_vector(31 downto 0);
    s 	: in std_logic_vector(1 downto 0);
    o		: out std_logic_vector(31 downto 0)
);
end mux3;

architecture behv of mux3 is
begin

  process(i0, i1, i2, s)
  begin
    case s is
	    when "00" 		=>	o <= i0;
	    when "01" 		=>	o <= i1;
		 when "10" 		=>	o <= i2;
		 when "11" 		=>	o <= (o'range => 'X');
	 end case;
  end process;

end behv;