--------------------------------------------------------------------
-- 2:1 multiplexor																--
--	myCPU																				--
-- Prof. Max Santana																--
--------------------------------------------------------------------

library ieee ;
use ieee.std_logic_1164.all;

entity mux2_5bits is
  port(	
    i0   : in std_logic_vector(4 downto 0);
	 i1   : in std_logic_vector(4 downto 0);
    s 	: in std_logic;
    o		: out std_logic_vector(4 downto 0)
);
end mux2_5bits;

architecture behv of mux2_5bits is
begin

  process(i0, i1, s)
  begin
    case s is
	    when '0' 		=>	o <= i0;
	    when '1' 		=>	o <= i1;
	 end case;
  end process;

end behv;