--------------------------------------------------------------------
-- Decoder																			--
--	myCPU																				--
-- Prof. Max Santana																--
--------------------------------------------------------------------

library ieee ;
use ieee.std_logic_1164.all;


entity decoder is
  port(	
    clock 	: in std_logic;
    reset 	: in std_logic;
	 
	 newPC	: in std_logic_vector(31 downto 0);
	 data		: in std_logic_vector(31 downto 0);
	 
	 pcWrite	: in std_logic;
    iord		: in std_logic;
    irwrite	: in std_logic;
	 memtoreg: in std_logic;
	 i			: in std_logic_vector(31 downto 0);
	 
	 npc		: out std_logic_vector(31 downto 0);
	 address	: out std_logic_vector(31 downto 0);
	 wd		: out std_logic_vector(31 downto 0);
	 
    op		: out std_logic_vector(5 downto 0); 	-- [31..26]
	 rs		: out std_logic_vector(4 downto 0); 	-- [25..21]
	 rt		: out std_logic_vector(4 downto 0); 	-- [20..16]
	 rd		: out std_logic_vector(4 downto 0); 	-- [15..11]
	 shamt	: out std_logic_vector(4 downto 0); 	-- [10..6]
	 funct	: out std_logic_vector(5 downto 0); 	-- [5..0]
	 imm		: out std_logic_vector(15 downto 0); 	-- [15..0]
	 addr		: out std_logic_vector(25 downto 0)		-- [25..0]	 
  );
end decoder;

architecture behv of decoder is
  component reg32
    port(	
      d     	: in std_logic_vector(31 downto 0);
      clock 	: in std_logic;
      reset 	: in std_logic;
	   load 	   : in std_logic;
      q			: out std_logic_vector(31 downto 0)
    );
  end component;
  
  component mux2_32bits
    port(	
      i0   	: in std_logic_vector(31 downto 0);
	   i1   	: in std_logic_vector(31 downto 0);
      s 		: in std_logic;
      o		: out std_logic_vector(31 downto 0)
    );
  end component;
  
  component instructionreg 
    port(	
      clock 	: in std_logic;
      reset 	: in std_logic;
	   load 	: in std_logic;
      i			: in std_logic_vector(31 downto 0);
	   op		: out std_logic_vector(5 downto 0); 	-- [31..26]
	   rs		: out std_logic_vector(4 downto 0); 	-- [25..21]
	   rt    		: out std_logic_vector(4 downto 0); 	-- [20..16]
	   rd		: out std_logic_vector(4 downto 0); 	-- [15..11]
	   shamt	: out std_logic_vector(4 downto 0); 	-- [10..6]
	   funct	: out std_logic_vector(5 downto 0); 	-- [5..0]
	   imm		: out std_logic_vector(15 downto 0); 	-- [15..0]
	   addr		: out std_logic_vector(25 downto 0)		-- [25..0]
    );
  end component;
  
  signal w_q			: std_logic_vector(31 downto 0);
  signal w_i			: std_logic_vector(31 downto 0);

begin

  pc : reg32 port map(
    clock 	=> clock,
	 reset 	=> reset,
	 load		=> pcWrite,
	 d			=> newPC,
	 q			=> w_q
  );
  
  mux1 : mux2_32bits port map(
	 i0		=> w_q,
	 i1		=> data,
	 s			=> iord,
	 o			=> address
  );
  
  mdr : reg32 port map(
    clock 	=> clock,
	 reset 	=> reset,
	 load		=> '1',
	 d			=> i,
	 q			=> w_i
  );
  
  mux2 : mux2_32bits port map(
	 i0		=> data,
	 i1		=> w_i,
	 s			=> memtoreg,
	 o			=> wd
  );
  
  ir	:	instructionreg port map(
    clock 	=> clock,
    reset 	=> reset,
	 load 	=> irwrite,
    i			=> i,
	 op		=> op,
	 rs		=> rs,
	 rt    	=> rt,
	 rd		=> rd,
	 shamt	=> shamt,
	 funct	=> funct,
	 imm		=> imm,
	 addr		=> addr
  );

  npc <= w_q;  

end behv;