--------------------------------------------------------------------
-- Decoder																			--
--	myCPU																				--
-- Prof. Max Santana																--
--------------------------------------------------------------------

library ieee ;
use ieee.std_logic_1164.all;


entity control is
  port(
    clock 			: in std_logic;
    reset 			: in std_logic;
	 op				: in std_logic_vector(5 downto 0);
	 zero 			: in std_logic;
	 irWrite			: out std_logic;
	 aluSrcA			: out std_logic;
	 aluSrcb			: out std_logic_vector(1 downto 0);
	 aluOp			: out std_logic_vector(1 downto 0);
	 iord				: out std_logic;
	 memWrite		: out std_logic;
	 memToReg		: out std_logic;
	 regWrite		: out std_logic;
	 regDst			: out std_logic;
	 pcWrite		 	: out std_logic;
	 pcSource		: out std_logic_vector(1 downto 0);
	 state			: out std_logic_vector(3 downto 0)
  );
end control;

architecture behv of control is

  type FSM is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, s11);

  signal current_state, next_state: FSM;
  
  signal w_pcWrite		: std_logic;
  signal w_pcWriteCond	: std_logic;
  

begin

  process(clock, reset)
  begin
    if (reset = '1') then
	   current_state <= S0;
	 elsif (clock = '1' and clock'event) then
	   current_state <= next_state;
		case(current_state) is
	     when S0 => state <= "0000";
		  when S1 => state <= "0001";
		  when S2 => state <= "0010";
		  when S3 => state <= "0011";
		  when S4 => state <= "0100";
		  when S5 => state <= "0101";
		  when S6 => state <= "0110";
		  when S7 => state <= "0111";
		  when S8 => state <= "1000";
		  when S9 => state <= "1001";
		  when S10 => state <= "1010";
		  when S11 => state <= "1011";
		end case; 
	 end if;    
  end process;
 
  process(current_state)
  begin
    case(current_state) is
	   when S0 =>
		  memWrite 		<= '0';
		  irwrite		<= '1';
	     aluSrcA		<= '0';
	     iord			<= '0';
	     aluSrcB		<= "01";
	     aluOp			<= "00";
	     w_pcWrite		<= '1';
	     pcSource  	<= "00";
		  w_pcwritecond <= '0';
		  pcwrite	  	<= (w_pcwrite or (w_pcwritecond and zero));
		  regdst			<= 'X';
		  memtoreg		<= 'X';
		  regwrite		<= '0';
	     
	     next_state <= S1;
	   when S1 =>
		  memWrite 		<= '0';
		  irwrite		<= '1';
	     aluSrcA		<= '0';
	     iord			<= 'X';
	     aluSrcB		<= "11";
	     aluOp			<= "00";
	     w_pcWrite		<= '0';
	     pcSource  	<= "XX";
		  w_pcwritecond <= '0';
		  pcwrite	  	<= (w_pcwrite or (w_pcwritecond and zero));
		  regdst			<= 'X';
		  memtoreg		<= 'X';
		  regwrite		<= '0';
		  
		  
		  case (op) is
	       when "000000" =>			   
		      next_state <= S6;
		    when "100011" | "101011" =>
		      next_state <= S2;
		    when "000100" =>
		      next_state <= S8;
		    when "000010" =>
		      next_state <= S9;
		    when "001000" =>
		      next_state <= S10;
		    when others =>
		      next_state <= S0; 
        end case;
		          
		  
	   when S2 =>
        memWrite 		<= '0';
		  irwrite		<= '1';
	     aluSrcA		<= '1';
	     iord			<= 'X';
	     aluSrcB		<= "10";
	     aluOp			<= "00";
	     w_pcWrite		<= '0';
	     pcSource  	<= "XX";
		  w_pcwritecond <= '0';
		  pcwrite	  	<= (w_pcwrite or (w_pcwritecond and zero));
		  regdst			<= 'X';
		  memtoreg		<= 'X';
		  regwrite		<= '0';
		  
		  if (op = "100011") then		  
			 next_state <= S3;
		  elsif (op = "101011") then
		    next_state <= S5; 
		  end if;  
	   when S3 =>
		  memWrite 		<= '0';
		  irwrite		<= '1';
	     aluSrcA		<= '1';
	     iord			<= '1';
	     aluSrcB		<= "10";
	     aluOp			<= "00";
	     w_pcWrite		<= '0';
	     pcSource  	<= "XX";
		  w_pcwritecond <= '0';
		  pcwrite	  	<= (w_pcwrite or (w_pcwritecond and zero));
		  regdst			<= 'X';
		  memtoreg		<= 'X';
		  regwrite		<= '0';
		
        
		  next_state 	<= S4;
		when S4 =>
		  memWrite 		<= '0';
		  irwrite		<= '1';
	     aluSrcA		<= '1';
	     iord			<= '1';
	     aluSrcB		<= "10";
	     aluOp			<= "00";
	     w_pcWrite		<= '0';
	     pcSource  	<= "XX";
		  w_pcwritecond <= '0';
		  pcwrite	  	<= (w_pcwrite or (w_pcwritecond and zero));
		  regdst			<= '0';
		  memtoreg		<= '1';
		  regwrite		<= '1';
		  
		  next_state 	<= S0;
		when S5 =>
		  memWrite 		<= '1';
		  irwrite		<= '1';
	     aluSrcA		<= '1';
	     iord			<= '1';
	     aluSrcB		<= "10";
	     aluOp			<= "00";
	     w_pcWrite		<= '0';
	     pcSource  	<= "XX";
		  w_pcwritecond <= '0';
		  pcwrite	  	<= (w_pcwrite or (w_pcwritecond and zero));
		  regdst			<= 'X';
		  memtoreg		<= 'X';
		  regwrite		<= '0';
		  
		  next_state 	<= S0;
		when S6 =>
		  memWrite 		<= '0';
		  irwrite		<= '1';
	     aluSrcA		<= '1';
	     iord			<= 'X';
	     aluSrcB		<= "00";
	     aluOp			<= "10";
	     w_pcWrite		<= '0';
	     pcSource  	<= "XX";
		  w_pcwritecond <= '0';
		  pcwrite	  	<= (w_pcwrite or (w_pcwritecond and zero));
		  regdst			<= 'X';
		  memtoreg		<= 'X';
		  regwrite		<= '0';
		  
        next_state 	<= S7;
		when s7 =>
		  memWrite 		<= '0';
		  irwrite		<= '1';
	     aluSrcA		<= '1';
	     iord			<= 'X';
	     aluSrcB		<= "00";
	     aluOp			<= "10";
	     w_pcWrite		<= '0';
	     pcSource  	<= "XX";
		  w_pcwritecond <= '0';
		  pcwrite	  	<= (w_pcwrite or (w_pcwritecond and zero));
		  regdst			<= '1';
		  memtoreg		<= '0';
		  regwrite		<= '1';

		  next_state 	<= S0;
		when s8 =>
		  memWrite 		<= '0';
		  irwrite		<= '1';
	     aluSrcA		<= '1';
	     iord			<= 'X';
	     aluSrcB		<= "00";
	     aluOp			<= "01";
	     w_pcWrite		<= '0';
	     pcSource  	<= "01";
		  w_pcwritecond <= '1';
		  pcwrite	  	<= (w_pcwrite or (w_pcwritecond and zero));
		  regdst			<= 'X';
		  memtoreg		<= 'X';
		  regwrite		<= '0';
		  
		  next_state 		<= S0;
		when s9 =>
		  memWrite 		<= '0';
		  irwrite		<= '1';
	     aluSrcA		<= 'X';
	     iord			<= 'X';
	     aluSrcB		<= "XX";
	     aluOp			<= "XX";
	     w_pcWrite		<= '1';
	     pcSource  	<= "10";
		  w_pcwritecond <= '0';
		  pcwrite	  	<= (w_pcwrite or (w_pcwritecond and zero));
		  regdst			<= 'X';
		  memtoreg		<= 'X';
		  regwrite		<= '0';
		  
		  next_state 	<= S0;
		when s10 =>
		  memWrite 		<= '0';
		  irwrite		<= '1';
	     aluSrcA		<= '1';
	     iord			<= 'X';
	     aluSrcB		<= "10";
	     aluOp			<= "00";
	     w_pcWrite		<= '0';
	     pcSource  	<= "XX";
		  w_pcwritecond <= '0';
		  pcwrite	  	<= (w_pcwrite or (w_pcwritecond and zero));
		  regdst			<= 'X';
		  memtoreg		<= 'X';
		  regwrite		<= '0';
		  
		  next_state 	<= S11;
		when S11 =>
        memWrite 		<= '0';
		  irwrite		<= '1';
	     aluSrcA		<= '1';
	     iord			<= 'X';
	     aluSrcB		<= "10";
	     aluOp			<= "00";
	     w_pcWrite		<= '0';
	     pcSource  	<= "XX";
		  w_pcwritecond <= '0';
		  pcwrite	  	<= (w_pcwrite or (w_pcwritecond and zero));
		  regdst			<= '0';
		  memtoreg		<= '0';
		  regwrite		<= '1';
		  
		  next_state 	<= S0;
	 end case;
  end process;   

end behv;